1. Field of the Invention
The present invention relates to methods for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device, which can prevent a threshold voltage of the semiconductor device from dropping caused by infiltration of dopant (impurity) of polysilicon from a cell region into an active channel region.
2. Discussion of the Related Art
In general, in the semiconductor memories, there are volatile memories, and non-volatile memories. Most of the volatile memories are RAMs, such as DRAM (Dynamic Random Access Memory), and SRAM (Static Random Access Memory), and so on, and can receive, and conserve data while power is applied, but can not conserve data when the power is cut off as the data volatilize. Opposite to this, the non-volatile memories, most of which are ROM (Read Only Memory), can conserve data even if no power is applied.
Presently, in view of fabrication process, in the non-volatile memories, there are a floating gate group, and an MIS (Metal Insulator Semiconductor) group in which two or more than two kinds of dielectric films are stacked in two or three layers.
The non-volatile memories in the floating gate group realize a memorizing performance by using a potential well, of which typical one is ETOX (EPROM Tunnel Oxide) which is widely used as a flash EEPROM (Electrically Erasable Programmable Read Only Memory), presently.
On the other hand, the non-volatile memories in the MIS group perform a memorizing function by using traps in a dielectric film bulk, an interface of dielectric films, and an interface of a dielectric film and a semiconductor, of which typical example is the MONOS/SONOS (Metal/Silicon ONO Semiconductor) structure mostly used as a flash EEPROM, presently.
Owing to the advantage of conservation of a stored data even if power is cut off, the non-volatile memories are widely used for storage of data for PC Bios, Set-Top Box, printer, and network server, and recently in digital camera, and cellular phone, and so on.
A related art method for fabricating a cell gate of an EEPROM flash memory, and a gate electrode of a peripheral circuit will be described. FIG. 1 illustrates a section showing infiltration of impurities into a silicon substrate.
Referring to FIG. 1, at first, an active cell isolation film (not shown) is formed in a semiconductor substrate 1 at a field region, to define an active region. An ONO (Oxide-Nitride-Oxide) layer 2 is formed on the silicon substrate, and first polysilicon 3 is coated on the ONO layer 2. Then, an insulating film 4 having a stack of an oxide film and a nitride film is formed on the first polysilicon 3.
Photoresist 5 is coated on the insulating film 4, and patterned by exposure and development. Then, the insulating film 4, the first polysilicon 3, and the ONO layer 2 are removed selectively by using the patterned photoresist 5 as a mask, to form a floating gate at the cell region. Then, the photoresist is removed.
Next, the silicon substrate 1 is subjected to thermal oxidation, to form a gate oxide film 6 at a logical circuit region. The thermal oxidation is performed at an elevated temperature in an N2 gas environment. Then, second polysilicon (not shown) is coated on above structure, and patterned, to form gate electrodes at the cell region and the logical circuit region, respectively. The first polysilicon 3 is doped polysilicon.
However, the related art method for fabricating an EEPROM flash memory has the following problems.
That is, because N2 gas is used in formation of the gate oxide film at the logical circuit region by thermal oxidation, dopant makes out diffusion from the first polysilicon to infiltrate into the silicon substrate to act as impurities. The impurities 7 present at a channel region of a transistor in the logical circuit region drops a threshold voltage.